Portions of circuits are often dedicated to protecting the circuits from damage due to electrostatic discharge (ESD). For example, in some cases one or more diode can be used to protect against ESD damage.
It is often necessary for the drain of a large NMOS output stage to handle voltages above the supply voltages of the chip. However, in such a circuit, a conventional ESD diode connected to its own positive supply rail can not be used. Accordingly, additional ESD clamp circuits are often added, e.g., as shown in FIG. 1.
Referring to FIG. 1, an NMOS output stage 102 is shown as including an open drain NMOS transistor (M4), having a gate receiving a drive signal from a drive circuit 104, a source connected to ground (GND), and a drain connected to an output bond pad 106. The transistor (M4) is preferably relatively large, e.g., sufficiently large so it can carry one-half an amp or more. The output bond pad 106 is shown as being connected to the cathode of a laser diode 108 (e.g., a blu-ray laser diode), and the anode of the laser diode 108 is shown as being connected to a voltage rail 110 (e.g., 8V) that is at a potential higher than the VCC voltage supply rail (e.g., VCC=5V). In this configuration, when the transistor (M4) is off, resulting in substantially no current flowing through the laser diode 108, the drain of transistor (M4) will be at about 6 or 7V.
Still referring to FIG. 1, an ESD clamp circuit 1141 is connected between a VCC bond pad 112 and ground, to provide ESD protection for circuits connected to the VCC bond pad 112. Also shown in FIG. 1 is a diode (D1) and a further ESD claim circuit 1142 (details of which are the same or similar to the ESD claim circuit 1141), connected between the output bond pad 106 and ground, to provide ESD protection for circuits (such as output stage 102) connected to the output bond pad 106.
In the example shown, the ESD clamp circuit 114 includes a relatively large NMOS transistor (M3), which acts as a switching circuit 116. The transistor (M3) includes a source connected to GND and a drain connected to a bond pad (e.g., VCC bond pad 112 for clamp circuit 1141, or output bond pad 106 for clamp circuit 1142). The ESD clamp circuit 114 also includes a PMOS transistor (M1) and NMOS transistor (M2), which form an inverter circuit 118. Like the transistor (M4), the transistor (M3) can preferably carry one-half an amp or more. Transistors (M1) and (M2) have their drains connected together and to the gate of transistor (M3). The source of the PMOS transistor (M1) is connected to the bond pad, and the source of the NMOS transistor (M2) is connected to GND. Additionally, the ESD clamp circuit 114 includes a time constant circuit 120. The time constant circuit includes a resistor (R1) and a capacitor (C1) connected in series between the bond pad and GND. The gates of the transistors (M1) and (M2) are connected to a node between the resistor (R1) and the capacitor (C1). The time constant circuit is used to define the turn-on of the transistor (M3).
The resistor (R1) and the capacitor (C1) of the time constant circuit 120 are arranged such that the ESD clamp circuit 114 turns on in response to the slew rate (i.e., dV/dt) of the bond pad to which it is connected. For example, if during an ESD event the voltage at the output bond pad 106 shoots up rapidly, the time constant circuit 120 provides a low voltage to the gates of the transistors (M1) and (M2) of the inverter circuit, causing transistor (M1) to turn on, and transistor (M2) to turn off. This will cause the transistor (M3) to be driven, and the transistor (M3) will sink the ESD to GND.
While the ESD solution of FIG. 1 works, providing a separate ESD clamp circuit 114 for each and every output stage that must operate above the chip's VCC (where there are multiple output stages) takes up a significant amount of chip area, e.g., due to the two or more relatively large transistors (M4) and (M3). Additionally, it is costly to provide a separate entire ESD clamp circuit for each separate output stage. Accordingly, the solution of FIG. 1 is price and space prohibitive. Further, parasitic capacitances of the ESD clamp circuit 1142 connected between the output bond pad 106 and GND adversely affects the performance of the output state 102. Thus, it would be beneficial if a better solution were provided.